Intel® Agilex™ F-Series and I-Series General-Purpose I/O User Guide

ID 683780
Date 6/14/2022
Public

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2.2.1. Supported I/O Standards for GPIO Banks

The VCCIO_PIO and VCCPT power supplies power the Intel® Agilex™ GPIO buffers. Each I/O bank has its own VCCIO_PIO power supply and supports only one I/O voltage.

The True Differential Signaling I/O standard is compatible with the LVDS, RSDS, Mini-LVDS, and LVPECL standards at a lower signal swing.

You can place the True Differential Signaling input buffer in a GPIO bank powered by 1.2 V and 1.5 V VCCIO_PIO. The maximum input voltage to the True Differential Signaling input buffer must not exceed the value of :
  • For 1.5V VCCIO_PIO bank, the maximum input voltage is 1.7 V
  • For 1.2V VCCIO_PIO bank, the maximum input voltage is 1.4 V

By default, the Intel® Quartus® Prime software assigns 1.2 V to the VCCIO_PIO pin in unused I/O banks. To assign 0 V, 1.2 V, or 1.5 V I/O standards to the pin, specify the assignment in the .qsf file located in your design directory.

Table 2.   Intel® Agilex™ GPIO Bank Supported I/O StandardsThis table lists the input and output voltages of a GPIO bank.
I/O Standard VCCIO_PIO (V) VCCPT (V) VREF (V) VTT (V) JEDEC Standard
Input Output
1.2 V LVCMOS 1.2 1.2 1.8 JESD-12A.01
SSTL-12 1.2 1.2 1.8 0.6 0.6 JESD79-4B
HSTL-12 1.2 1.2 1.8 0.6 0.6 JESD-16A
HSUL-12 1.2 1.2 1.8 0.6 JESD209-3C
POD12 1.2 1.2 1.8 Internally calibrated 1.2 JESD79-4B
Differential SSTL-12 1 1.2 1.2 1.8 0.6 JESD79-4B
Differential HSTL-12 1 1.2 1.2 1.8 0.6 JESD8-16A
Differential HSUL-12 1 1.2 1.2 1.8 JESD209-3C
Differential POD-12 1 1.2 1.2 1.8 Internally calibrated 1.2 JESD79-4B
True Differential Signaling 2 1.2/1.5 1.5 1.8
1 Uses two single-ended outputs with second output programmed as inverted.
2 True Differential Signaling input buffers are powered by 1.8 V VCCPT

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