Intel® Agilex™ F-Series and I-Series General-Purpose I/O User Guide

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ID 683780
Date 6/14/2022
Public
Document Table of Contents

6.2.6. OCT Intel® FPGA IP Architecture

Figure 49.  OCT IP Top-Level DiagramThis figure shows the top-level diagram of the OCT IP.
Table 61.   OCT IP Components
Component Description
RZQ pin

There are two RZQ pins in each GPIO bank. The RZQ pin shares the same VCCIO supply with the I/O bank where the pin is located.

RZQ pins are dual-purpose pins.

  • If the pins are not connected to the OCT block, you can use the pins as regular I/O pins.
  • If you use the RZQ pin for OCT, the pin connects to an external reference resistor to calculate the calibration codes to implement the required impedance. The RZQ pin connects the OCT block to ground through an external 240 Ω resistor with a precision of ±1%.
OCT block

The OCT block generates and sends calibration code words to the I/O buffer blocks.

  • There are two OCT blocks in each GPIO bank. The OCT blocks generates calibration codes to terminate the I/Os.
  • During calibration, the OCT matches the impedance seen on the external resistor through the rzqin port. Then, the OCT block generates calibration code words and sends to the I/O buffer through ser_data ports.

OCT Intel FPGA IP Power-Up Mode Interfaces

The OCT IP in power-up mode has two main interfaces.
  • One input interface connecting the FPGA RZQ pad to the OCT block
  • One output interface that connects to the I/O buffers.
Figure 50.  OCT Interfaces

OCT Intel FPGA IP User Mode OCT

The Fitter does not infer a user-mode OCT. To use the OCT block for user mode calibration, you must generate the OCT IP. The IP uses the calibration_request and ack_recal signals to send and receive calibration request from the core.

The FPGA core initiates a calibration request to the OCT IP by asserting the calibration_request signal to high for at least 2 µs. The OCT IP asserts the ack_recal signal to the core to indicate that the IP has received the request.

You can only use the OCT IP in user mode with the GPIO IP. Connect the terminationcontrol signal from the GPIO IP to the ser_data signal in the OCT IP using RTL connections or TERMINATION_CONTROL_BLOCK .qsf assignment.

Figure 51.  OCT Intel® FPGA IP User Mode Connections
Note: A single OCT IP can control up to 12 OCT blocks.

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