Intel® Agilex™ F-Series and I-Series General-Purpose I/O User Guide

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ID 683780
Date 6/14/2022
Public
Document Table of Contents

6.1.4.4. Data Interface Signals and Corresponding Clocks

Table 48.  Data Interface Signals and Corresponding Clocks
Signal Name Parameter Configuration Clock Signal Name
Register mode Half Rate logic Separate input/output Clocks
din
  • Simple Register
  • DDIO
Off Off ck
DDIO On Off ck_hr
  • Simple Register
  • DDIO
Off On ck_in
DDIO On On ck_hr_in
  • dout
  • oe
  • Simple Register
  • DDIO
Off Off ck
DDIO On Off ck_hr
  • Simple Register
  • DDIO
Off On ck_out
DDIO On On ck_hr_out
  • sclr
  • sset
  • All pad signals
  • Simple Register
  • DDIO
Off Off ck
DDIO On Off ck_fr
  • Simple Register
  • DDIO
Off On
  • Input path: ck_in
  • Output path: ck_out
DDIO On On
  • Input path: ck_fr_in
  • Output path: ck_fr_out

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