3.4.2. HPS I/O Pins During Power Sequencing
Adhere to the these guidelines to prevent unnecessary current draw on the I/O pins located in the HPS I/O banks. These guidelines apply for unpowered, power up to POR, POR delay, POR delay to configuration, configuration, initialization, user mode, and power down device states.
- The I/O pins in the HPS I/O banks can be tri-stated, driven to ground, or driven to the VCCIO_HPS level.
- While the Intel® Agilex™ device is powering up or down, the input signals of an I/O pin, at all times, must not exceed the I/O buffer power supply rail of the bank where the I/O pin resides.
- While the Intel® Agilex™ device is powering up, powering down, or not turned on, the HPS I/O pins can tolerate a maximum of 10 mA per pin and a total of 100 mA per HPS I/O bank.
- After the Intel® Agilex™ device fully powers up, the voltage levels for the HPS I/O pins must not exceed the DC input voltage (VI) value.
|The VCCIO_HPS pin ramps up and at period X, the VCCIO_HPS voltage is 0.9 V.||At period X, keep the signals driven by the device connected to the HPS I/O pin at a voltage of 0.9 V or lower.|
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