Intel® Agilex™ F-Series and I-Series General-Purpose I/O User Guide

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ID 683780
Date 6/14/2022
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6.1.4. GPIO Intel® FPGA IP Interface Signals

Depending on the parameter settings you specify, different interface signals are available for the GPIO IP.
Figure 30.  GPIO IP Interfaces


Figure 31.  GPIO Interface Signals
Table 43.  Pad Interface SignalsThe pad interface is the physical connection from the GPIO IP to the pad. This interface can be an input, output or bidirectional interface, depending on the IP configuration. In this table, SIZE is the data width specified in the IP parameter editor.
Signal Name Direction Description
pad_in[SIZE-1:0] Input

Input signal from the pad.

pad_in_b[SIZE-1:0] Input

Negative node of the differential input signal from the pad. This port is available if you turn on the Use differential buffer option.

pad_out[SIZE-1:0] Output Output signal to the pad.
pad_out_b[SIZE-1:0] Output

Negative node of the differential output signal to the pad. This port is available if you turn on the Use differential buffer option.

pad_io[SIZE-1:0] Bidirectional

Bidirectional signal connection with the pad.

pad_io_b[SIZE-1:0] Bidirectional

Negative node of the differential bidirectional signal connection with the pad. This port is available if you turn on the Use differential buffer option.

Table 44.  Data Interface SignalsThe data interface is an input or output interface from the GPIO IP to the FPGA core. In this table, SIZE is the data width specified in the IP parameter editor.
Signal Name Direction Description
din[DATA_SIZE-1:0] Input

Data input from the FPGA core in output or bidirectional mode. DATA_SIZE depends on the register mode:

  • Bypass or simple register— DATA_SIZE = SIZE
  • DDIO without half-rate logic— DATA_SIZE = 2 × SIZE
  • DDIO with half-rate logic— DATA_SIZE = 4 × SIZE
dout[DATA_SIZE-1:0] Output

Data output to the FPGA core in input or bidirectional mode, DATA_SIZE depends on the register mode:

  • Bypass or simple register— DATA_SIZE = SIZE
  • DDIO without half-rate logic— DATA_SIZE = 2 × SIZE
  • DDIO with half-rate logic— DATA_SIZE = 4 × SIZE
oe[OE_SIZE-1:0] Input

OE input from the FPGA core in output mode with Enable output enable port turned on, or bidirectional mode. OE is active high. When transmitting data, set this signal to 1. When receiving data, set this signal to 0. OE_SIZE depends on the register mode:

  • Bypass or simple register— DATA_SIZE = SIZE
  • DDIO without half-rate logic— DATA_SIZE = SIZE
  • DDIO with half-rate logic— DATA_SIZE = 2 × SIZE

For ×4 DQ group implementation, refer to the related information.

Table 45.  Clock Interface SignalsThe clock interface is an input clock interface. It consists of different signals, depending on the configuration. The GPIO IP can have zero, one, two, or four clock inputs. Clock ports appear differently in different configurations to reflect the actual function performed by the clock signal.
Signal Name Direction Description
ck Input

In input and output paths, this clock feeds a packed register or DDIO if you turn off the Half Rate logic parameter.

In bidirectional mode, this clock is the unique clock for the input and output paths if you turn off the Separate input/output Clocks parameter.

ck_fr Input

In input and output paths, these clocks feed the full-rate and half-rate DDIOs if your turn on the Half Rate logic parameter.

In bidirectional mode, the input and output paths use these clocks if you turn off the Separate input/output Clocks parameter.

ck_hr
ck_in Input

In bidirectional mode, these clocks feed a packed register or DDIO in the input and output paths if you specify both these settings:

  • Turn off the Half Rate logic parameter.
  • Turn on the Separate input/output Clocks parameter.
ck_out
ck_fr_in Input

In bidirectional mode, these clocks feed a full-rate and half-rate DDIOs in the input and output paths if you specify both of these settings:

  • Turn on the Half Rate logic parameter.
  • Turn on the Separate input/output Clocks parameter.

For example, ck_fr_out feeds the full-rate DDIO in the output path.

ck_fr_out
ck_hr_in
ck_hr_out
cke Input Clock enable.

For ×4 DQ group implementation, refer to the related information.

Table 46.  Termination Interface SignalsThe termination interface connects the GPIO IP to the I/O buffers.
Signal Name Direction Description
terminationcontrol Input Input from the termination control block (OCT) to the buffers. It sets the buffer series and parallel impedance values.
Table 47.  Reset Interface SignalsThe reset interface connects the GPIO IP core to the DDIOs. For ×4 DQ group implementation, refer to the related information.
Signal Name Direction Description
sclr Input

Synchronous clear input. Not available if you select None or Preset for the Enable synchronous clear / preset port option.

aclr Input

Asynchronous clear input. Active high. Not available if you select None or Preset for the Enable asynchronous clear / preset port option.

aset Input

Asynchronous set input. Active high. Not available if you select None or Clear for the Enable asynchronous clear / preset port option.

sset Input Synchronous set input. Not available if you select None or Clear for the Enable synchronous clear / preset port option.

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