Intel® Agilex™ F-Series and I-Series General-Purpose I/O User Guide

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ID 683780
Date 6/14/2022
Public
Document Table of Contents

2.1.2. I/O Buffers and Registers

The I/O registers consist of three different paths.
  • The input path for handling data from the pin to the core
  • The output path for handling data from the core to the pin
  • The output enable (OE) path for handling the OE signal to the output buffer

The I/O registers allow fast source-synchronous register-to-register transfers and resynchronizations. To use the I/O registers to implement DDR circuitry, you can use the GPIO Intel® FPGA IP.

The input and output paths contain the following blocks:

  • Input registers:
    • Support half or full rate data transfer from the periphery to the core
    • Support double or single data rate data captured from I/O buffer
  • Output registers:
    • Support half or full rate data transfer from the core to the periphery
    • Support double or single data rate data transfer to I/O buffer
  • OE registers:
    • Support the output enable signal from the core to the periphery
    • Support double data rate or single data rate data transfer to I/O buffer

The input and output paths also support the following features:

  • Clock enable
  • Asynchronous or synchronous reset
  • Bypass mode for input and output paths
  • Delay chain on input and output paths
Figure 3. I/O Element (IOE) Structure for Intel® Agilex™ Devices

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