Intel® Agilex™ F-Series and I-Series General-Purpose I/O User Guide

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ID 683780
Date 6/14/2022
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4.2.3. I/O Standards and Features for Intel® Agilex™ Configuration Pins

The SDM pins have different I/O standards and features in different Intel® Agilex™ configuration schemes. You can assign the unused SDM pins for other functions in the Intel® Quartus® Prime software.
Table 29.   Intel® Agilex™ AS ×4 Configuration Scheme—Dedicated Configuration Pins
Pin Function SDM I/O Direction I/O Standard Schmitt Trigger/TTL Input Weak Pull-Up/Pull-Down Drive Strength Open Drain Slew Rate
AS_DATA1 SDM_IO1 Bidirectional 1.8 V LVCMOS Schmitt Trigger Disable 8 mA Disable Fast
AS_CLK SDM_IO2 Output 1.8 V LVCMOS 8 mA Disable Fast
AS_DATA2 SDM_IO3 Bidirectional 1.8 V LVCMOS Schmitt Trigger Disable 8 mA Disable Fast
AS_DATA0 SDM_IO4 Bidirectional 1.8 V LVCMOS Schmitt Trigger Disable 8 mA Disable Fast
AS_nCSO0 SDM_IO5 Output 1.8 V LVCMOS 8 mA Disable Fast
AS_DATA3 SDM_IO6 Bidirectional 1.8 V LVCMOS Schmitt Trigger Disable 8 mA Disable Fast
AS_nCSO2 SDM_IO7 Output 1.8 V LVCMOS 8 mA Disable Fast
AS_nCSO3 SDM_IO8 Output 1.8 V LVCMOS 8 mA Disable Fast
AS_nCSO1 SDM_IO9 Output 1.8 V LVCMOS 8 mA Disable Fast
AS_nRST SDM_IO15 Output 1.8 V LVCMOS 8 mA Disable Fast
Table 30.   Intel® Agilex™ AS ×4 Configuration Scheme—Unused Configuration PinsFor the unused configuration pins, the drive strength, open drain, and slew rate settings are not applicable.
SDM I/O Direction I/O Standard Schmitt Trigger/TTL Input Weak Pull-Up/Pull-Down
SDM_IO0 Input 1.8 V LVCMOS Schmitt Trigger Weak pull-down with 20 kΩ resistor
SDM_IO10 Input 1.8 V LVCMOS Schmitt Trigger Weak pull-up with 20 kΩ resistor
SDM_IO11 Input 1.8 V LVCMOS Schmitt Trigger Weak pull-up with 20 kΩ resistor
SDM_IO12 Input 1.8 V LVCMOS Schmitt Trigger Weak pull-up with 20 kΩ resistor
SDM_IO13 Input 1.8 V LVCMOS Schmitt Trigger Weak pull-up with 20 kΩ resistor
SDM_IO14 Input 1.8 V LVCMOS Schmitt Trigger Weak pull-up with 20 kΩ resistor
SDM_IO16 Input 1.8 V LVCMOS Schmitt Trigger Weak pull-down with 20 kΩ resistor
Table 31.   Intel® Agilex™ Avalon® Streaming Interface ×8 Configuration Scheme—Dedicated Configuration Pins
Pin Function SDM I/O Direction I/O Standard Schmitt Trigger/TTL Input Weak Pull-Up/Pull-Down Drive Strength Open Drain Slew Rate
AVSTx8_DATA2 SDM_IO1 Input 1.8 V LVCMOS Schmitt Trigger Disable
AVSTx8_DATA0 SDM_IO2 Input 1.8 V LVCMOS Schmitt Trigger Disable
AVSTx8_DATA3 SDM_IO3 Input 1.8 V LVCMOS Schmitt Trigger Disable
AVSTx8_DATA1 SDM_IO4 Input 1.8 V LVCMOS Schmitt Trigger Disable
AVSTx8_DATA4 SDM_IO6 Input 1.8 V LVCMOS Schmitt Trigger Disable
AVSTx8_READY SDM_IO8 Output 1.8 V LVCMOS 8 mA Disable Fast
AVSTx8_DATA7 SDM_IO10 Input 1.8 V LVCMOS Schmitt Trigger Disable
AVSTx8_VALID SDM_IO11 Input 1.8 V LVCMOS Schmitt Trigger Weak pull-down with 20 kΩ resistor
AVSTx8_DATA5 SDM_IO13 Input 1.8 V LVCMOS Schmitt Trigger Disable
AVSTx8_CLK SDM_IO14 Input 1.8 V LVCMOS Schmitt Trigger Disable
AVSTx8_DATA6 SDM_IO15 Input 1.8 V LVCMOS Schmitt Trigger Disable
Table 32.   Intel® Agilex™ Avalon® Streaming Interface ×8 Configuration Scheme—Unused Configuration PinsFor the unused configuration pins, the drive strength, open drain, and slew rate settings are not applicable.
SDM I/O Direction I/O Standard Schmitt Trigger/TTL Input Weak Pull-Up/Pull-Down
SDM_IO0 Input 1.8 V LVCMOS Schmitt Trigger Weak pull-down with 20 kΩ resistor
SDM_IO5 Input 1.8 V LVCMOS Schmitt Trigger Weak pull-up with 20 kΩ resistor
SDM_IO7 Input 1.8 V LVCMOS Schmitt Trigger Weak pull-up with 20 kΩ resistor
SDM_IO9 Input 1.8 V LVCMOS Schmitt Trigger Weak pull-up with 20 kΩ resistor
SDM_IO12 Input 1.8 V LVCMOS Schmitt Trigger Weak pull-up with 20 kΩ resistor
SDM_IO16 Input 1.8 V LVCMOS Schmitt Trigger Weak pull-down with 20 kΩ resistor
Table 33.   Intel® Agilex™ Avalon® Streaming Interface ×16 or ×32 Configuration Scheme—Dedicated Configuration PinsFor all pin functions in this table:
  • The I/O location is the SDM shared GPIO bank.
  • The weak pull-up or pull-down, and open drain options are not applicable.
Pin Function Direction I/O Standard Drive Strength Slew Rate
AVST_CLK Input 1.2 V LVCMOS
AVST_READY Output 1.2 V LVCMOS

Series 34 Ω OCT without calibration

Slow
AVST_VALID Input 1.2 V LVCMOS
AVST_DATA Input 1.2 V LVCMOS
Table 34.   Intel® Agilex™ Optional Configuration PinsThe SDM I/O for each pin function in this table is as assigned in the Intel® Quartus® Prime configuration pins option.
Pin Function Direction I/O Standard

Schmitt Trigger/

TTL Input

Weak Pull-Up / Pull-Down Drive Strength Open Drain Slew Rate
PWRMGT_SCL Bidirectional 1.8V LVCMOS Schmitt Trigger Weak pull-up with 20 kΩ resistor 2 mA Enable Slow
PWRMGT_SDA Bidirectional 1.8V LVCMOS Schmitt Trigger Weak pull-up with 20 kΩ resistor 2 mA Enable Slow
PWRMGT_ALERT Output 1.8V LVCMOS 2 mA Enable Slow
CONF_DONE Output 1.8V LVCMOS 8 mA Disable Fast
INIT_DONE Output 1.8V LVCMOS 8 mA Disable Fast
CvP_CONFDONE Output 1.8V LVCMOS 8 mA Disable Fast
SEU_ERROR Output 1.8V LVCMOS 8 mA Disable Fast
HPS_COLD_nRESET Bidirectional 1.8V LVCMOS Schmitt Trigger Weak pull-up with 20 kΩ resistor 2 mA Enable Fast
Direct to factory image Input 1.8V LVCMOS Schmitt Trigger Weak pull-down with 20 kΩ resistor
nCATTRIP Output 1.8V LVCMOS 2 mA Disable Slow
TAMPERDETECTION Output 1.8V LVCMOS 8 mA Disable Fast
TAMPERRESPONSESTATUS Output 1.8V LVCMOS 8 mA Disable Fast

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