Intel® Agilex™ F-Series and I-Series General-Purpose I/O User Guide

ID 683780
Date 6/14/2022
Public
Document Table of Contents

7. Programmable I/O Features Description

Table 62.  I/O Features and Description
I/O Features Description
Programmable Output Slew Rate Control

Each I/O pin contains a slew rate control, allowing you to specify the slew rate on a pin-by-pin basis. The slew rate control affects both the rising and falling edges of the signal.

A faster slew rate provides high-speed transitions for high-performance systems while a slower slew rate reduces system noise and crosstalk but adds a nominal delay to the rising and falling edges.

Programmable IOE Delay

You can activate the programmable IOE delays to ensure zero hold time, minimize setup time, or increase the clock-to-output time. This feature helps read and write timing margins because it minimizes the uncertainties between signals on the bus.

Each pin can have a different input delay from the pin-to-input register or a delay from output register-to-output pin values. This is to ensure that the signals within a bus have the same delay going into or out of the device.

Programmable Open-Drain Output

The programmable open-drain output provides a high-impedance state on output when logic to the output buffer is high. If logic to the output buffer is low, the output is low.

You can attach several open-drain outputs to a wire. This connection type is like a logical OR function and is commonly called an active-low wired-OR circuit. If at least one of the outputs is in logic 0 state (active), the circuit sinks the current and brings the line to low voltage.

You can use open-drain output if you are connecting multiple devices to a bus. For example, you can use the open-drain output for system-level control signals that can be asserted by any device or as an interrupt.

Programmable Bus-Hold

Each I/O pin supports an optional bus-hold feature that is active only after configuration. When the device enters user mode, the bus-hold circuit captures the value that is present on the pin by the end of the configuration.

The bus-hold circuitry uses a resistor to weakly pull the signal level to the last-driven state of the pin. The bus-hold circuitry holds this pin state until the next input signal is present. Therefore, you do not require an external pull-up or pull-down resistor to hold a signal level when the bus is tri-stated.

For each I/O pin, you can individually specify that the bus-hold circuitry pulls non-driven pins away from the input threshold voltage—where noise can cause unintended high-frequency switching. To prevent over-driving signals, the bus-hold circuitry drives the voltage level of the I/O pin lower than the I/O bank power supply level.

Programmable Pull-Up Resistor

Each I/O pin on supported banks provides an optional programmable pull-up resistor during user mode. The pull-up resistor weakly holds the I/O to the I/O bank power supply level.

Programmable Pull-Down Resistor

Each I/O pin on supported banks provides an optional programmable pull-down resistor during user mode. The pull-down resistor weakly holds the I/O to the ground level.

Programmable Pre-Emphasis

Pre-emphasis momentarily boosts the high-frequency component of the output signal during switching to increase the output slew rate. The amount of pre-emphasis required depends on the attenuation of the high-frequency component along the transmission line.

For more information, refer to Programmable Pre-Emphasis.

Programmable De-Emphasis

De-emphasis attenuates the I/O signal height when the symbol is longer than the specified duration. You can use de-emphasis to alter the signal amplitude to compensate for signal degradation over long transmission path.

For more information, refer to Programmable De-Emphasis.

Programmable Differential Output Voltage

The programmable VOD settings allow you to adjust the output eye-opening to optimize the trace length and power consumption. A higher VOD swing improves voltage margins at the receiver end, and a smaller VOD swing reduces power consumption.

For more information, refer to Programmable Differential Output Voltage.

Schmitt Trigger

The Schmitt Trigger allows input buffers to respond to slow input edge rates with a fast output edge rate. Most importantly, Schmitt Triggers provide hysteresis on the input buffer, preventing slow-rising noisy input signals from ringing or oscillating on the input signal driven into the logic array.

This feature provides system noise tolerance on the device inputs but adds a small, nominal input delay.

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