Intel® Agilex™ F-Series and I-Series General-Purpose I/O User Guide

ID 683780
Date 6/14/2022
Public

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5. Intel® Agilex™ I/O Troubleshooting Guidelines

These debug guidelines are initial debug actions and do not necessarily resolve the failures in your designs.
Table 37.  GPIO Debug GuidelinesThis table lists the failure symptoms and the associated debug actions that you can take to identify the failure areas when you are designing GPIO systems with Intel® Agilex™ devices.
Failure Symptoms Recommended Debug Actions

1.2 V LVCMOS output at the entire bank does not reach 1.2 V.

  • Check the power-up and power-down sequences of each voltage rail with respect to time.
  • Compare the power sequences as per recommendation in the Intel® Agilex™ Power Management User Guide.
  • Verify the VCCIO_PIO voltage signal is 1.2 V.

Intel® Quartus® Prime software shows an error message to indicate incorrect I/O settings for VCCIO during design compilation.

Error message example: Illegal constraint of I/O bank to the location <I/O bank>

Select the I/O pins specified in the error message and check the I/O settings for the pins.

Intel® Quartus® Prime software shows illegal I/O error message during design compilation.

Error message example: Programmable VOD option is set to 1 for pin <pin_name>, but setting is not supported by <I/O standard>

Select the I/O pins specified in the error message and set the pins to the correct I/O function. Refer to the device pin-outs file for more information about the pin functions.

Unable to configure a pin as an open-drain output pin.

  • Ensure that the pin is set to the correct voltage specification per the device data sheet.
  • To ensure the pin is correctly set to open-drain output, check the compilation report or the resource property editor.

Unable to configure a pin to use the bus-hold feature.

Ensure that the pin is not set to programmable pull-up resistor. The bus-hold feature is not available when the pin is set to programmable pull-up resistor.

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