Intel® Agilex™ F-Series and I-Series General-Purpose I/O User Guide

ID 683780
Date 6/14/2022

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2.5.9. HPS Shared I/O Requirements

The HPS EMIF uses I/O pins located in the GPIO bank instead of the HPS I/O bank. The 1.2 V VCCIO_PIO powers the GPIO bank instead of the 1.8 V VCCIO_HPS. For the location of the HPS shared GPIO pins, refer to device pin-out files.