Intel® Agilex™ F-Series and I-Series General-Purpose I/O User Guide

ID 683780
Date 6/14/2022

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

2.6. I/O Simulation

Intel provides three types of simulation models for Intel® Agilex™ devices.

These simulation models are:

  • Synopsys* HSPICE* models
  • IBIS models
  • IBIS AMI models
Table 19.  Simulation Models Descriptions
Model Supported I/O Type Description
  • Simulates actual transistor level design to obtain precise electrical simulation.
  • The syntax describes I/O buffers, board components and connections, and specific simulation parameters.
  • The model contains encrypted transistor and logic cell library models, output buffer circuit models for single-ended and differential I/Os, and sample SPICE decks for single-ended and differential I/Os.
  • The model requires a longer simulation time compared to the IBIS model.
  • This is a behavioral model of the I/O buffers based on the I/V curve data derived from the HSPICE* simulation.
  • The pre-emphasis feature is an example that can use the IBIS simulation model.
  • This model has a shorter simulation time compared to HSPICE* .
  • The simulation model has less complexity compared to HSPICE* models and supported by many simulation tools.
IBIS AMI Transceiver I/O
  • Algorithmic Modeling Interface (IBIS AMI) is a part of IBIS 5.0 specification for high-speed transmitter and receiver models that are supplied as executables in tools that support IBIS simulation.
  • This is an industry standard model methodology for high-speed link simulation applied to multi gigabit serial link channels.
  • This simulation model allows simulation of millions of bits in minutes, crosstalk and jitter analysis, detect data pattern dependencies, and able to model complex blocks such as equalization and CDR.