Intel® Agilex™ F-Series and I-Series General-Purpose I/O User Guide

ID 683780
Date 6/14/2022

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Document Table of Contents Timing Analysis

The Intel® Quartus® Prime software does not automatically generate the SDC timing constraints for the GPIO IP. You must manually enter the timing constraints.

Follow the timing guidelines and examples to ensure that the Timing Analyzer analyzes the I/O timing correctly.

  • To perform proper timing analysis for the I/O interface paths, specify the system level constraints of the data pins against the system clock pin in the .sdc file.
  • To perform proper timing analysis for the core interface paths, define these clock settings in the .sdc file:
    • Clock to the core registers
    • Clock to the I/O registers for the simple register and DDIO modes