Intel® Agilex™ F-Series and I-Series General-Purpose I/O User Guide

ID 683780
Date 6/14/2022
Public
Document Table of Contents

2.2.2. GPIO Buffer Behavior

Table 3.   GPIO Pins Guideline for Different Pin States
GPIO Pin State
Not turned on Powering up Fully powered up Configuration mode User mode Powering down

Pin voltage must not exceed VCCIO_PIO or 1.2 V, whichever is lower.

  • Pin voltage must not exceed VCCIO_PIO or 1.2 V, whichever is lower.
  • After full VCC power up, the pins are tri-stated with weak pull-up enabled.

All pins are tri-stated with weak pull-up enabled.

All pins are tri-stated with weak pull-up enabled.

Valid data transactions can be initiated.

  • Pin voltage must not exceed VCCIO_PIO or 1.2 V, whichever is lower.
  • When the VCCIO_PIO and VCC power rails are powering down, the I/O pin signals measure between ground and the VCCIO_PIO voltage levels.
Note: After the Intel® Agilex™ device fully powers up, input signals of the I/O pins must not exceed the maximum DC input voltage specified in the device data sheet.

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