Intel® MAX® 10 Analog to Digital Converter User Guide

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ID 683596
Date 5/04/2021
Public
Document Table of Contents

5.5.1. Sequencer Core Registers

Table 35.  Command Register (CMD)

Address Offset: 0x0

Bit Name Attribute Description Value Default
31:4 Reserved Read Reserved. 0
3:1 Mode Read-Write

Indicates the operation mode of the sequencer core.

These bits are ignored when the run bit (bit 0) is set.

In continuous conversion, the data will be overwritten after a complete sampling sequence.

  • 7—Recalibrate the ADC
  • 6 to 2—Reserved
  • 1—Single cycle ADC conversion
  • 0—Continuous ADC conversion
0
0 Run Read-Write

Use this control bit to trigger the sequencer core operation.

The Modular ADC Core IP core waits until the sequencer core completes its current operation before writing to this register bit.

  • 1—Run
  • 0—Stop
0

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