Intel® MAX® 10 Analog to Digital Converter User Guide

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ID 683596
Date 5/04/2021
Public
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2.2.2. Modular ADC Core and Modular Dual ADC Core IP Cores Architecture

The Modular ADC Core IP core consists of six micro cores.
Table 6.   Modular ADC Core Micro Cores
Micro Core Description
ADC control

This core interacts with the ADC hard IP block. The ADC control core uses Avalon ST interface to receive commands from upstream cores, decodes, and drives the ADC hard IP block accordingly.

Sequencer

This core contains command register and static conversion sequence data. The sequencer core issues commands for downstream cores to execute.

  • You can use the command register to configure the intended conversion mode.
  • You can configure the length and content of the conversion sequence data only when generating the IP core.
  • You can access the register of the sequencer core through the Avalon-MM slave interface.
  • The command information to the downstream core goes through the Avalon ST interface.
Sample storage

This core stores the ADC samples that are received through the Avalon ST interface.

  • The samples are stored in the on-chip RAM. You can retrieve the samples through the Avalon-MM slave interface.
  • With this core, you have the option to generate interrupt when the ADC receives a block of ADC samples (one full round of conversion sequence).
Response merge

This core merges simultaneous responses from two ADC control cores into a single response packet to send to the sample storage core. This core is available only if you use the Modular Dual ADC Core IP core in the following configurations:

  • Standard Sequencer with Avalon-MM Sample Storage
  • Standard Sequencer with Avalon-MM Sample Storage and Threshold Violation Detection
Dual ADC synchronizer core

This core performs synchronization handshakes between two ADC control cores. This core is available only if you use the Modular Dual ADC Core IP core.

Threshold detection
  • This core supports fault detection. The threshold detection core receives ADC samples through the Avalon ST interface and checks whether the samples value exceeds the maximum or falls below the minimum threshold value.
  • The threshold detection core conveys threshold value violation information through the Avalon ST interface.
  • You can configure which channel to enable for maximum and minimum threshold detection and the threshold values only during IP core generation.

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