2.2.2. Modular ADC Core and Modular Dual ADC Core IP Cores Architecture
This core interacts with the ADC hard IP block. The ADC control core uses Avalon ST interface to receive commands from upstream cores, decodes, and drives the ADC hard IP block accordingly.
This core contains command register and static conversion sequence data. The sequencer core issues commands for downstream cores to execute.
This core stores the ADC samples that are received through the Avalon ST interface.
This core merges simultaneous responses from two ADC control cores into a single response packet to send to the sample storage core. This core is available only if you use the Modular Dual ADC Core IP core in the following configurations:
|Dual ADC synchronizer core||
This core performs synchronization handshakes between two ADC control cores. This core is available only if you use the Modular Dual ADC Core IP core.
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