Intel® MAX® 10 Analog to Digital Converter User Guide

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ID 683596
Date 5/04/2021
Public
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5.5.2. Sample Storage Core Registers

Table 36.  ADC Sample Register (ADC_SAMPLE) of Modular ADC Core

Address Offset: 0x3F (slot 64)—0x0 (slot 1)

Bit Name Attribute Description Value Default
31:12 Reserved Read

Reserved.

0
11:0 Sample Read The data sampled by the ADC for the corresponding slot. Sampled data 0
Table 37.  ADC Sample Register (ADC_SAMPLE) of Modular Dual ADC Core

Address Offset: 0x3F (slot 64)—0x0 (slot 1)

Bit Name Attribute Description Value Default
31:28 Reserved Read Reserved. 0
27:16 Sample Read The data sampled by ADC2 for the corresponding slot. Sampled data 0
15:12 Reserved Read Reserved. 0
11:0 Sample Read The data sampled by ADC1 for the corresponding slot. Sampled data 0
Table 38.  Interrupt Enable Register (IER)

Address Offset: 0x40

Clear the enable bit to prevent the corresponding interrupt status bit from causing interrupt output assertion (IRQ). The enable bit does not stop the interrupt status bit value from showing in the interrupt status register (ISR).

Bit Name Attribute Description Value Default
31:1 Reserved Read Reserved. 0
0 M_EOP Read-Write The enable bit for the end of packet (EOP) interrupt.
  • 1—Enables the corresponding interrupt
  • 0—Disables the corresponding interrupt
1
Table 39.  Interrupt Status Register (ISR)

Address Offset: 0x41

Bit Name Attribute Description Value Default
31:1 Reserved Read Reserved. 0
0 EOP Read-Write (one cycle) EOP interrupt. This bit is automatically set by the hardware. When "1", it indicates that a packet of samples is stored and ready to be read. You can retrieve the sample value from the ADC_SAMPLE register. To clear this bit to "0" for the next interrupt, write "1". 0

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