Intel® MAX® 10 Analog to Digital Converter User Guide

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ID 683596
Date 5/04/2021
Public
Document Table of Contents

2.5.1. Fixed ADC Logic Simulation Output

By default, the Enable user created expected output file option in the Modular ADC Core or Modular Dual ADC Core IP core is disabled. The ADC simulation always output a fixed value for each ADC channel, including the analog and TSD channels. The values are different for single and dual ADC devices.
Table 9.  Fixed Expected Output Data for Single ADC Device Simulation
Channel Expected Output Data (Decimal Value)
CH0 0
CH1 1
CH2 2
CH3 3
CH4 4
CH5 5
CH6 6
CH7 7
CH8 8
CH9 9
CH10 10
CH11 11
CH12 12
CH13 13
CH14 14
CH15 15
CH16 16
TSD 3615
Table 10.  Fixed Expected Output Data for Dual ADC Device Simulation
Channel Expected Output Data (Decimal Value)
ADC1 ADC2
CH0 10 20
CH1 11 21
CH2 12 22
CH3 13 23
CH4 14 24
CH5 15 25
CH6 16 26
CH7 17 27
CH8 18 28
TSD 3615

(No TSD in ADC2)

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