Intel® MAX® 10 Analog to Digital Converter User Guide

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ID 683596
Date 5/04/2021
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5.4.2. Response Interface of Modular ADC Core and Modular Dual ADC Core

The response interface is an Avalon-ST type interface that does not support backpressure. To avoid overflow condition at the source port, implement sink ports with response data process time that is fast enough, or with enough buffers storage.
Table 27.  Response Interface Signals
Signal Width (Bit) Description
valid 1 Indication from the source port that current transfer is valid.
channel 5

Indicates the ADC channel to which the ADC sampling data corresponds for the current response.

  • 31:18—not used
  • 17—temperature sensor
  • 16:0—channels 16 to 0; where channel 0 is the dedicated analog input pin and channels 1 to 16 are the dual purpose analog input pins
data 12 or 24

ADC sampling data:

  • 12 bit width for Modular ADC Core
  • 24 bit width for Modular Dual ADC Core
startofpacket 1

Indication from the source port that current transfer is the start of packet.

For altera_adc_control core implementation, the source of this signal is from the corresponding command interface.

endofpacket 1

Indication from the source port that current transfer is the end of packet.

For altera_adc_control core implementation, the source of this signal is from the corresponding command interface.

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