Intel® MAX® 10 Analog to Digital Converter User Guide

ID 683596
Date 5/04/2021
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5.4.1. Command Interface of Modular ADC Core and Modular Dual ADC Core

The command interface is an Avalon-ST type interface that supports a ready latency of 0.
Table 26.  Command Interface Signals
Signal Width (Bit) Description
valid 1 Indication from the source port that current transfer is valid.
ready 1 Indication from the sink port that it is ready for current transfer.
channel 5

Indicates the channel that the ADC hard block samples from for current command.

  • 31—recalibration request
  • 30:18—not used
  • 17—temperature sensor
  • 16:0—channels 16 to 0; where channel 0 is the dedicated analog input pin and channels 1 to 16 are the dual purpose analog input pins
startofpacket 1

Indication from the source port that current transfer is the start of packet.

  • For altera_adc_sequencer core implementation, the IP core asserts this signal during the first slot of conversion sequence data array.
  • For altera_adc_control core implementation, this signal is ignored. The IP core just passes the received information back to the corresponding response interface.
endofpacket 1

Indication from the source port that current transfer is the end of packet.

  • For altera_adc_sequencer core implementation, IP core asserts this signal during the final slot of conversion sequence data array.
  • For altera_adc_control core implementation, this signal is ignored. The IP core just passes the received information back to the corresponding response interface.

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