Intel® MAX® 10 Analog to Digital Converter User Guide

ID 683596
Date 5/04/2021

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Document Table of Contents ADC Control Core

The ADC control core drives the ADC hard IP according to the command it receives. The control core also maps the channels from the Modular ADC Core IP core to the channels in the ADC hard IP block.

The ADC control core of the Modular ADC Core IP core implements only the functions that are related to ADC hard IP block operations. For example:

  • Power up
  • Power down
  • Analog to digital conversion on analog pins
  • Analog to digital conversion on on-chip temperature sensor

The ADC control core has two clock domains:

  • One clock domain for clocking the ADC control core soft logic
  • Another clock domain for the ADC hard IP block

The ADC control core does not have run-time configurable options.

Figure 17. ADC Control Core High-Level Block Diagram

Table 7.  ADC Control Core Backpressure Behavior
Interface Backpressure Behavior

The ADC control core asserts ready when it is ready to perform a sample conversion.

The ADC control core only accepts one command at a time. The control core releases ready when it completes processing current command and prepares to perform the next command.

Once the ADC control core asserts "cmd_ready=1" to acknowledge the current command, the Sequencer core provides the next valid request within two clock cycles. If the next valid request comes after two clock cycles, the ADC control core perform non-continuous sampling.


The ADC control core does not support backpressure in the response interface. The fastest back-to-back assertion of valid request is 1 µs.