Intel® MAX® 10 Analog to Digital Converter User Guide

ID 683596
Date 5/04/2021

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

2.1.9. ADC Timing

Figure 8.  Intel® MAX® 10 ADC Control Core Timing DiagramThe following figure shows the timing diagram for the command and response interface of the Modular ADC Core control core. The timing diagram shows the latency of the first valid response data, and the latency between the first acknowledgment of the first command request and the back-to-back response data. The diagram shows an example where:
  • The conversion sequence is from channel 16 to channel 1 to channel 2
  • The response data for channel 16 is 8
  • The response data for channel 1 is 1