Intel® MAX® 10 Analog to Digital Converter User Guide

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ID 683596
Date 5/04/2021
Public
Document Table of Contents

2.2.2.2. Sequencer Core

The sequencer core controls the type of conversion sequence performed by the ADC hard IP. You can configure the conversion mode during run time using the sequencer core registers.

During Modular ADC Core or Modular Dual ADC Core IP core configuration, the sequencer core provides up to 64 configurable slots. You can define the sequence that the ADC channels are sampled by selecting the ADC channel for each sequencer slot.

The sequencer core has a single clock domain.

Figure 18. Sequencer Core High-Level Block Diagram


Table 8.  Sequencer Core Conversion Modes
Conversion Mode Description
Single cycle ADC conversion
  • In this mode, when the run bit is set, ADC conversion starts from the channel that you specify in the first slot.
  • The conversion continues onwards with the channel that you specify in each sequencer slot.
  • Once the conversion finishes with the last sequencer slot, the conversion cycle stops and the ADC hard IP block clears the run bit.
Continuous ADC conversion
  • In this mode, when the run bit is set, ADC conversion starts from the channel that you specify in the first slot.
  • The conversion continues onwards with the channel that you specify in each sequencer slot.
  • Once the conversion finishes with the last sequencer slot, the conversion begins again from the first slot of the sequence.
  • To stop the continuous conversion, clear the run bit. The sequencer core continues the conversion sequence until it reaches the last slot and then stops the conversion cycle.

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