Intel® MAX® 10 Analog to Digital Converter User Guide

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ID 683596
Date 5/04/2021
Public
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2.1.5. ADC Clock Sources

The ADC block uses the device PLL as the clock source. The ADC clock path is a dedicated clock path. You cannot change this clock path.

Depending on the device package, the Intel® MAX® 10 devices support one or two PLLs—PLL1 only, or PLL1 and PLL3.

For devices that support two PLLs, you can select which PLL to connect to the ADC. You can configure the ADC blocks with one of the following schemes:

  • Both ADC blocks share the same clock source for synchronization.
  • Both ADC blocks use different PLLs for redundancy.

If each ADC block in your design uses its own PLL, the Intel® Quartus® Prime Fitter automatically selects the clock source scheme based on the PLL clock input source:

  • If each PLL that clocks its respective ADC block uses different PLL input clock source, the Intel® Quartus® Prime Fitter follows your design (two PLLs).
  • If both PLLs that clock their respective ADC block uses the same PLL input clock source, the Intel® Quartus® Prime Fitter merges both PLLs as one.

In dual ADC mode, both ADC instance must share the same ADC clock setting.

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