Intel® MAX® 10 Analog to Digital Converter User Guide

ID 683596
Date 5/04/2021
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4.5. Completing ADC Design

The ADC design requires that the ALTPLL IP core clocks the Modular ADC Core IP core.
Generate the ALTPLL and Modular ADC Core IP cores with the settings in the related information.
Figure 30. Basic Intel® MAX® 10 ADC Design


  1. Create the design as shown in the preceding figure.
  2. Connect the c0 signal from the ALTPLL IP core to the adc_pll_clock_clk port of the Modular ADC Core IP core.
  3. Connect the locked signal from the ALTPLL IP core to the adc_pll_locked_export port of the Modular ADC Core IP core.
  4. Create the ADC Avalon slave interface to start the ADC.

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