Intel® MAX® 10 Analog to Digital Converter User Guide

ID 683596
Date 5/04/2021
Document Table of Contents Dual ADC Synchronizer Core

The dual ADC synchronizer core performs synchronization handshakes between two ADC control cores in the Modular Dual ADC Core IP core.

The peripheral clock domain is asynchronous to the ADC PLL clock domain in the ADC control core. Control event from the ADC hard IP block can appear at the peripheral clock domain at the same time, or by a difference of one peripheral clock between ADC1 and ADC2 control cores. Both ADC hard IP cores communicate with the dual ADC synchronizer core through the Avalon-ST interface.

For example, although a new command valid event from the sequencer arrives at both ADC control cores at the same peripheral clock cycle, the end of conversion signals arrive at one peripheral clock cycle difference between ADC1 and ADC2. To avoid the condition where ADC1 begins conversion earlier or later than ADC2, the ADC control core performs synchronization handshake using the dual ADC synchronizer core.

An ADC control core asserts a sync_valid signal when it detects an ADC PLL clock domain event. The dual ADC synchronizer core asserts the sync_ready signal after it receives sync_valid signals from both ADC control cores. After the sync_ready signal is asserted, both ADC control cores proceed to their next internal state.

Figure 21. Dual ADC Synchronizer Core High-Level Block Diagram

Did you find the information on this page useful?

Characters remaining:

Feedback Message