Intel® MAX® 10 Analog to Digital Converter User Guide

ID 683596
Date 5/04/2021
Document Table of Contents

5.4.4. CSR Interface of Modular ADC Core and Modular Dual ADC Core

The CSR interface is an Avalon-MM slave interface.
Table 29.  CSR Interface Signals
Signal Width (Bit) Description
address 1 or 7

Avalon-MM address bus. The address bus width is in the unit of word addressing:

  • altera_adc_sample_store core—address width is seven
  • altera_adc_sequencer core—address width is one
read 1

Avalon-MM read request.

write 1

Avalon-MM write request.

writedata 32

Avalon-MM write data bus.

readdata 32

Avalon-MM read data bus.

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