Intel® MAX® 10 Analog to Digital Converter User Guide

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ID 683596
Date 5/04/2021
Public
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4.2. Customizing and Generating Modular ADC Core IP Core

Intel recommends that you use the Modular ADC Core IP core with a Nios II processor, which supports the ADC HAL driver.
  1. Create a new project in the Intel® Quartus® Prime software.
    While creating the project, select a device that has one or two ADC blocks.
  2. In the Intel® Quartus® Prime software, select Tools > Qsys.
  3. In the Qsys window, select File > New System.
    A clock source block is automatically added under the System Contents tab.
  4. In the System Contents tab, double click the clock name.
  5. In the Parameters tab for the clock source, set the Clock frequency.
  6. In the IP Catalog tab in the Qsys window, double click Processors and Peripherals > Peripherals > Modular ADC Core .
    The Modular ADC Core appears in the System Contents tab and the Modular ADC Core parameter editor opens.
  7. In the Modular ADC Core parameter editor, specify the parameter settings and channel sampling sequence for your application.
  8. In the System Contents tab in the Qsys window, double click the Export column of the adc_pll_clock and adc_pll_locked interfaces to export them.
  9. Connect the clock, reset_sink, sample_store_csr, and sample_store_irq signals. Optionally, you can use the Nios II Processor, On-Chip Memory, and JTAG UART IP cores to form a working ADC system that uses the Intel FPGA ADC HAL drivers.
  10. In the Qsys window, select File > Save.
You can copy an example HDL code to declare an instance of your ADC system. In the Qsys window, select Generate > HDL Example.

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