Intel® MAX® 10 Analog to Digital Converter User Guide

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ID 683596
Date 5/04/2021
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4.3. Parameters Settings for Generating ALTPLL IP Core

Navigate through the ALTPLL IP core parameter editor and specify the settings required for your design. After you have specified all options as listed in the following table, you can generate the HDL files and the optional simulation files.

For more information about all ALTPLL parameters, refer to the related information.

Table 12.   ALTPLL Parameters SettingsTo generate the PLL for the ADC, use the following settings.
Tab Parameter Setting
Parameter Settings > General/Modes What is the frequency of the inclk0 input?

Specify the input frequency to the PLL.

Parameter Settings > Inputs/Lock Create an 'areset' input to asynchronously reset the PLL

Turn off this option.

Create 'locked' output

Turn on this option. You need to connect this signal to the adc_pll_locked port of the Modular ADC Core or Modular Dual ADC Core IP core.

Output Clocks > clk c0 Use this clock

Turn on this option.

Enter output clock frequency

Specify an output frequency of 2, 10, 20, 40, or 80 MHz. You can specify any of these frequencies. The ADC block runs at 1 MHz internally but it contains a clock divider that can further divide the clock by a factor of 2, 10, 20, 40, and 80.

Use this same frequency value in your Modular ADC Core or Modular Dual ADC Core IP core. You need to connect this signal to the adc_pll_clock port of the Modular ADC Core or Modular Dual ADC Core IP core.

Different ADC sampling rates support different clock frequencies. For a valid sampling rate and clock frequency combination, refer to the related information.

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