Agilex™ 7 Hard Processor System Technical Reference Manual

ID 683567
Date 8/13/2024
Public
Document Table of Contents

11.3.1.1. PLLs

The two PLLs in the clock manager generate the majority of clocks in the HPS. There is no phase control between the clocks generated by the two PLLs.

Each PLL has the following features:

  • Phase detector, output lock signal generation and configurable M/N VCO w/o fractional counter
  • Four output dividers with a range of 1 to 2047 to further subdivide the clock
  • A PLL can be configured to bypass all outputs to the input clock for glitch-free transitions