Agilex™ 7 Hard Processor System Technical Reference Manual

ID 683567
Date 8/13/2024
Public
Document Table of Contents

25.4.12.1. DAP

The DAP uses the system APB port to connect to the FPGA.

Table 222.  DAPThe following table shows the signal description between DAP and FPGA.
Signal Description
h2f_dbg_apb_PADDR Address bus to system APB port, when PADDR
h2f_dbg_apb_PADDR31 Address bus to system APB port, when PADDR31
h2f_dbg_apb_PENABLE Enable signal from system APB port
h2f_dbg_apb_PRDATA[32] 32-bit system APB port read data bus
h2f_dbg_apb_PREADY Ready signal to system APB port
h2f_dbg_apb_PSEL Select signal from system APB port
h2f_dbg_apb_PSLVERR Error signal to system APB port
h2f_dbg_apb_PWDATA[32] 32-bit system APB port write data bus
h2f_dbg_apb_PWRITE Select whether read or write to system APB port
  • 0 - System APB port read from DAP
  • 1 - System APB Port write to DAP