Intel Agilex® 7 Hard Processor System Technical Reference Manual

ID 683567
Date 1/11/2024
Public
Document Table of Contents

7.3.2. FPGA-to-HPS Fabric Bypass Mux

If the FPGA Fabric Bypass Mux is enabled, then:
  • FPGA-to-HPS bridge is not available for FPGA-to-CCU and FPGA-to-SDRAM traffic.
  • MPFE remains in reset.
  • SDRAM ECC is not available. But, SDRAM traffic can still be ECC protected using the soft logic.
  • FPGA-to-SDRAM access is managed in a similar manner like any other IO96 or IO96 pair from the FPGA.
  • The HPS-to-SDRAM path is routed through the HPS-to-FPGA port to the FPGA. It allows FPGA to control the SDRAM bandwidth allocation as well as in-line encryption for SDRAM traffic.