Intel Agilex® 7 Hard Processor System Technical Reference Manual

ID 683567
Date 1/11/2024
Public
Document Table of Contents

5.5. System Memory Management Unit Configuration

You must configure the SMMU TBUs to prevent coherent master transactions from accessing the HPS-to-SDM mailbox address range. Only the Cortex*-A53 CPUs have access to the 256 byte HPS-to-SDM mailbox range.
  • The 256-byte HPS-to-SDM mailbox that must be protected starts at address 0xFFA30000 and ends at 0xFFA300FF.
  • Enable the SMMU to translate from virtual to physical address (stage 1 translation).
  • Configure the page tables for your TBU so that it issues a context fault if a master attempts to access the HPS-to-SDM mailbox range. There are two ways you can communicate a page table context fault:
    • Use interrupts that route through the generic interrupt controller (GIC). Set the CFIE bit of the TBU's context bank system control register (SMMU_CB*_SCTLR) to enable interrupt reporting of a context fault. Program your software to sample the corresponding context interrupt, cxt_irpt_*. Note that the CFIE bit clears on reset. The SMMU contains 32 context banks and 32 corresponding interrupts in the GIC.
    • Generate a slave error on the AXI bus as the response sent back to the master. Set the CFRE bit of the context bank system control register (SMMU_CB*_SCTLR) to enable an abort bus error when a context fault occurs. Note that CFRE bit clears on reset.