Agilex™ 7 Hard Processor System Technical Reference Manual

ID 683567
Date 8/13/2024
Public
Document Table of Contents

3.5.4.2. Data Cache

The data cache is 4-way set associative with a cache line length of 64 bytes. It is organized as a physically indexed and physically tagged cache. The micro TLB for the data cache converts virtual addresses to physical addresses before it executes a cache access.

  • Supports 256-bit writes and 128-bit reads to L2 cache
  • Utilizes prefetch engine and read buffer
  • Supports three outstanding data cache misses
  • Provides error checking and correction (ECC) on L1 data and parity checking on control bits