Intel Agilex® 7 Hard Processor System Technical Reference Manual

ID 683567
Date 1/11/2024
Public
Document Table of Contents

23.2. Timers Block Diagram and System Integration

Each timer includes a slave interface for control and status register (CSR) access, a register block, and a programmable 32‑bit down counter that generates interrupts on reaching zero. The timer operates on a single clock domain driven by the clock manager.
Figure 126. Timers Block Diagram