Agilex™ 7 Hard Processor System Technical Reference Manual

ID 683567
Date 8/13/2024
Public
Document Table of Contents

15.5.2.1. Erase Operations

Before data can be written to flash, an erase cycle must occur. The NAND flash memory controller supports single block and multi‑plane erases.

The controller decodes the block address from the indirect addressing shown in "MAP10 Command Format".