Agilex™ 7 Hard Processor System Technical Reference Manual

ID 683567
Date 8/13/2024
Public
Document Table of Contents

25.4.14. Debug Resets

Table 226.  CoreSight Resets

ARM Reset Name

Clock Source

HPS Reset Signal Name

Description

ARESETn Reset manager dbg_rst_n

STM AXI slave and DMA peripheral request block reset.

STMRESETn Reset manager dbg_rst_n Resets the rest of the STM including the APB, HW EVT block, and the TGU block.
ATRESETn

Reset manager

dbg_rst_n

Trace bus reset. It resets all registers in the ATCLK domain.

CTIRESETn

(from the CTI)

Reset manager

dbg_rst_n

CTI reset signal. It resets all registers in the CTICLK domain.

CTIRESETn

(from the FPGA-CTI)

Reset manager

dbg_rst_n

CTI reset signal. It resets all registers in the CTICLK domain. In the HPS, there are four instances of CTI. All four use the same reset signal.

PRESETDBGn Reset manager dbg_rst_n

Connected to the A53 CPUs. Connected to DAP AXI Reset

PRESETDBGn

Reset manager

cs_dap_rst_n

Debug APB reset. Connected to DAP AXI Reset.

RESETn

Reset manager

Debug APB reset. Resets all registers clocked by PCLKDBG.

PRESETSYSn

Reset manager

dbg_rst_n

Resets system APB slave port of DAP.

nCTMRESET

Reset manager

dbg_rst_n

CTM reset signal. It resets all signals clocked by CTMCLK.

nPOTRST

Reset manager

 

True power on reset signal to the DAP SWJ-DP. It must only reset at power-on.

TRESETn

Reset manager

dbg_rst_n

Reset signal for TPIU. Resets all registers in the TRACECLKIN domain.

timestamp timestamp reset

GEN CPU TS. APB reset- sys_dbg_rst_n.

Trace Timestamp:
  • APB reset (resetn) - dbg_rst_n
  • timestamp reset - dbg_rst_n

The ETR stall enable field (etrstallen) of the ctrl register in the reset manager controls whether the ETR is requested to stall its AXI master interface to the L3 interconnect before a warm or debug reset.

The level 4 (L4) watchdog timers can be paused during debugging to prevent reset while the processor is stopped at a breakpoint.

For more information about the CoreSight port names, refer to the CoreSight Technology System Design Guide on the Arm* Infocenter website.