Agilex™ 7 Hard Processor System Technical Reference Manual

ID 683567
Date 8/13/2024
Public
Document Table of Contents

9.3.7. On-Chip RAM Resets

During a cold or warm reset, the contents of the RAM remain unchanged. The reset only clears the state on the AXI bus.

Name Functional Usage Comments
ram_rst_n RAM AXI interconnect reset Asynchronously asserted, synchronously de-asserted to osc1_clk