Agilex™ 7 Hard Processor System Technical Reference Manual

ID 683567
Date 8/13/2024
Public
Document Table of Contents

17.4.4. PHY Interface Options

The table below identifies the signals used for each PHY interface selected.
Table 171.  PHY Interface Options
Port Name MII 39 GMII39 RMII40 SGMII41
emac_phy_txd_o[7:0] Yes, [3:0] Yes, [7:0] Yes, [1:0] Yes, [7:0]
emac_phy_mac_speed_o 42 Yes Yes Yes Yes
emac_phy_txen_o Yes Yes Yes Yes
emac_phy_txer_o 42 No Yes No Yes, part of transmit code
emac_phy_rxdv_i Yes Yes Yes Yes, part of receive code
emac_phy_rxer_i 42 Yes Yes No Yes, part of receive code
emac_phy_rxd_i[7:0] Yes, [3:0] Yes, [7:0] Yes, [1:0] Yes, [7:0]
emac_phy_col_i 42 Yes Yes No No
emac_phy_crs_i 42 Yes Yes No No
emac_clk_rx_i Yes Yes Yes Yes
emac_clk_tx_i 42 Yes Yes No Yes
emac_phy_txclk_o No Yes No Yes
emac_rst_clk_tx_n_o 42 Yes Yes No No
emac_rst_clk_rx_n_o 42 Yes Yes No No
emac_gmii_mdc_o Yes Yes Yes Yes

emac_gmii_mdo_o,

emac_gmii_mdo_o_e,

emac_gmii_mdi_i 43

Yes Yes Yes Yes
emac_ptp_pps_o 44 Yes Yes No No
emac_ptp_aux_ts_trig_i 44 Yes Yes No No
39 Default HPS EMAC interface for export to FPGA.
40 This option requires the Intel FPGA MII to RMII Converter Core.
41 This option requires the Intel FPGA HPS GMII to TSE 1000BASE-X/SGMII PCS Bridge Core
42 This signal is only available through the FPGA interface.
43 These three signals make up the MDIO output signal.
44 This is an optional signal.