Agilex™ 7 Hard Processor System Technical Reference Manual

ID 683567
Date 8/13/2024
Public
Document Table of Contents

9.3.2. On-Chip RAM Controller

The on-chip RAM is a single-port memory that is composed of:
  • Five FIFOs that register inputs and outputs on the AXI4 bus. Each of the five FIFOs correspond to an AXI4 channel:
    • Write address
    • Write data
    • Write response
    • Read address
    • Read data
  • Each FIFO holds two entries to support the on-chip RAM's memory acceptance. The FIFO indicates to the slave bus when it is ready to accept another entry.
  • Arbiter—The SRAM is a single-port design which means that only one read or one write can be executed in any given clock. The Arbiter grants either read or write access to the memory in a round-robin fashion.