Agilex™ 7 Hard Processor System Technical Reference Manual

ID 683567
Date 8/13/2024
Public
Document Table of Contents

17.4.3.1. MDIO Interface

The MDIO interface signals are synchronous to l4_mp_clk in all supported modes.

Note: The MDIO interface signals can be routed to both the FPGA and HPS I/O.
Table 170.  MDIO Interface Signals (Routed to FPGA I/O)
Signal Name Width Direction Description Default Value for Inputs Recommended Tie-off
emac<2:0>_gmii_mdi_i 1 Input Management Data In. The PHY generates this signal to transfer register data during a read operation. This signal is driven synchronously with the gmii_mdc_o clock. 1'b1 Pull-up
emac<2:0>_gmii_mdo_o 1 Output Management Data Out. The EMAC uses this signal to transfer control and data information to the PHY.
emac<2:0>_gmii_mdo_o_e 1 Output Management Data Output Enable. This signal is asserted whenever valid data is driven on the gmii_mdo_o signal and can be used as a tri-state control for the gmii_mdo_o Fabric I/O tri-state output buffers. The active state of this signal is high.
emac<2:0>_gmii_mdc_o 1 Output Management Data Clock. The EMAC provides timing reference for the gmii_mdi_i and gmii_mdo_o signals on MII through this a periodic clock. The maximum frequency of this clock is 2.5 MHz. This clock is generated from the application clock through a clock divider.