Agilex™ 7 Hard Processor System Technical Reference Manual

ID 683567
Date 8/13/2024
Public
Document Table of Contents

17.1.3. Management Interface

  • 32‑bit host interface to CSR set
  • Comprehensive status reporting for normal operation and transfers with errors
  • Configurable interrupt options for different operational conditions
  • Per-frame transmit/receive complete interrupt control
  • Separate status returned for transmission and reception packets
  • Big endian and little endian configurable support for transmission and reception data paths