Agilex™ 7 Hard Processor System Technical Reference Manual

ID 683567
Date 8/13/2024
Public
Document Table of Contents

16.4.3.3. Clock Control Block

The clock control block provides different clock frequencies required for SD/MMC/CE‑ATA cards. The clock control block has one clock divider, which is used to generate different card clock frequencies.

The clock frequency of a card depends on the following clock ctrl register settings:

  • clkdiv register—Internal clock dividers are used to generate different clock frequencies required for the cards. The division factor for the clock divider can be set by writing to the clkdiv register. The clock divider is an 8‑bit value that provides a clock division factor from 1 to 510; a value of 0 represents a clock‑divider bypass, a value of 1 represents a divide by 2, a value of 2 represents a divide by 4, and so on.
  • clksrc register—Set this register to 0 as clock is divided by clock divider 0.
  • clkena register—The cclk_out card output clock can be enabled or disabled under the following conditions:
    • cclk_out is enabled when the cclk_enable bit in the clkena register is set to 1 and disabled when set to 0.
    • Low‑power mode can be enabled by setting the cclk_low_power bit of the clkena register to 1. If low‑power mode is enabled to save card power, the cclk_out signal is disabled when the card is idle for at least eight card clock cycles. Low‑power mode is enabled when a new command is loaded and the command path goes to a non-idle state.

Under the following conditions, the card clock is stopped or disabled:

  • Clock can be disabled by writing to the clkena register.
  • When low‑power mode is selected and the card is idle for at least eight clock cycles.
  • FIFO buffer is full, data path cannot accept more data from the card, and data transfer is incomplete—to avoid FIFO buffer overflow.
  • FIFO buffer is empty, data path cannot transmit more data to the card, and data transfer is incomplete—to avoid FIFO buffer underflow.
Note: The card clock must be disabled through the clkena register before the host software changes the values of the clkdiv and clksrc registers.