Agilex™ 7 Hard Processor System Technical Reference Manual

ID 683567
Date 8/13/2024
Public
Document Table of Contents

13.4.2. Watchdog Reset Sequence

A watchdog timeout event triggers this reset sequence. Reset Manager asserts watchdog reset based on the watchdog timer register.

  1. Reset Manager performs L2FLUSH, if enabled.
    1. Use the Reset_Mgr.mpul2flushtimeout register to timeout L2FLUSH event. The default value of the register is 0x00100000.
  2. Reset Manager performs the following handshakes:
    1. L2 cache handshaking, if enabled using the Reset_Mgr.hdsken.l2flushen register.
    2. FPGA handshaking, if enabled using the Reset_Mgr.hdsken.fpgasen register.
    3. ETR handshaking, if enabled using the Reset_Mgr.hdsken.etrstallen register.
    4. HMC handshaking, if enabled using the Reset_Mgr.hdsken.mpfe_hmca_drainen register.
  3. Reset Manager initiates boot mode request handshake with Clock Manager.
  4. Reset Manager waits for an acknowledgement signal from Clock Manager that indicates completion of the boot mode handshake before proceeding any further.
    • A cold reset request that occurs before the completion of this step takes precedence over the watchdog reset sequence.
    • A cold reset request that occurs after the completion of this step is delayed until the watchdog reset is completed.
  5. Reset Manager asserts Watchdog reset.
  6. After a definite time-period, Reset Manager de-asserts all modules in reset except MPU.
  7. Reset Manager waits until the Reset_Mgr.ocramload.done bit is set.
  8. Reset Manager de-asserts L2/SCU using the Reset_Mgr.coldmodrst.l2 register bit.
  9. Reset Manager de-asserts MPU cores using the Reset_Mgr.mpumodrst.core[3:0] and Reset_Mgr.coldmodrst.cpupor[3:0] register bits.
  10. You can de-assert peripheral modules using the Reset_Mgr.per0modrst and Reset_Mgr.per1modrst registers.