Intel Agilex® 7 Hard Processor System Technical Reference Manual

ID 683567
Date 1/11/2024
Public
Document Table of Contents

20.5.5.5. Receive Watermark Level

Similar to choosing the transmit watermark level described earlier, the receive watermark level, IC_ DMA_RDLR + 1, should be set to minimize the probability of overflow, as shown in the Receive FIFO Buffer diagram. It is a trade off between the number of DMA burst transactions required per block versus the probability of an overflow occurring. †