Intel Agilex® 7 Hard Processor System Technical Reference Manual

ID 683567
Date 1/11/2024
Public
Document Table of Contents

3.5.4.2.1. ACE Transactions

The L1 ACE Data Transactions that are supported are listed in the table below. Refer to the Arm* Cortex* -A53 MPCore Processor Technical Reference Manual for more details.
Table 34.  L1 ACE Data Transactions
Attribute ACE Transaction
Memory Type Shareability Domain Load Store Load Exclusive Store Exclusive
Device N/A System ReadNoSnoop WriteNoSnoop ReadNoSnoop and ARLOCKM set to HIGH WriteNoSnoop and AWLOCKM set to HIGH
Normal, inner Non-cacheable, outer Non-cacheable Non-shared System ReadNoSnoop WriteNoSnoop ReadNoSnoop and ARLOCKM set to HIGH WriteNoSnoop and AWLOCKM set to HIGH
Inner-shared
Outer-shared
Normal, inner Non-cacheable, outer Write-Back or Write-Through Non-shared System ReadNoSnoop WriteNoSnoop ReadNoSnoop ReadNoSnoop
Inner-shared System ReadNoSnoop WriteNoSnoop ReadNoSnoop and ARLOCKM set to HIGH WriteNoSnoop and AWLOCKM set to HIGH
Outer-shared
Normal, inner Write-Through, outer Write-Back, Write-Through Non-shared System ReadNoSnoop WriteNoSnoop ReadNoSnoop ReadNoSnoop
Inner-shared System ReadNoSnoop WriteNoSnoop ReadNoSnoop and ARLOCKM set to HIGH WriteNoSnoop and AWLOCKM set to HIGH
Outer-shared
Non-cacheable, or Normal inner Write-Back outer Non-cacheable or Write-Through Non-shared System ReadNoSnoop WriteNoSnoop ReadNoSnoop ReadNoSnoop
Inner-shared System ReadNoSnoop WriteNoSnoop ReadNoSnoop with ARLOCKM set to HIGH WriteNoSnoop with ARLOCKM set to HIGH
Outer-shared
Normal, inner Write-Back, outer Write-Back Non-shared Non-shareable ReadNoSnoop WriteNoSnoop ReadNoSnoop WriteNoSnoop
Inner-shared Inner Shareable ReadShared ReadUnique or CleanUnique if required, then a WriteBack when the line is evicted ReadShared with ARLOCKM set to HIGH CleanUnique with ARLOCKM set to HIGH if required, then a WriteBack when the line is evicted
Outer-shared Outer Shareable
Note: It is recommended that no load or store instructions are placed between the exclusive load and the exclusive store because these additional instructions can cause a cache eviction. Any data cache maintenance instruction can also clear the exclusive monitor.