Agilex™ 7 Hard Processor System Technical Reference Manual

ID 683567
Date 8/13/2024
Public
Document Table of Contents

17.4.1. EMAC Controller I/O Signals

There are three EMACs available in the HPS. The following table lists the EMAC signals that can be routed from the EMACs to the HPS I/O pins. These signals provide the RMII/RGMII interface.

Table 168.  EMAC Controller Interface Signals (Routed to HPS I/O)
Signal Name Width Direction Description Default Value for Inputs Recommended Tie-off
EMAC<2:0>_TX_CLK 1 Output

This signal provides the transmit clock for RGMII (125/25/2.5 MHz in 1G/100M/10Mbps).

This signal is one option for the common transmit and receive clock in RMII mode (50 MHz for both 10 Mbps or 100 Mbps mode). The other possible source for the common transmit and receive clock is an external clock source, in which case EMACn_TX_CLK is left unconnected. In RMII mode, if this signal is the clock source for the receiver, then connect EMACn_TX_CLK to EMACn_RX_CLK.

All PHY transmit signals generated by the EMAC are synchronous to this clock.

EMAC<2:0>_TXD[3:0] 4 Output

This group of transmit data signals is driven by the MAC. Bits [3:0] provide the RGMII transmit data, and bits [1:0] provide the RMII transmit data. In RGMII 1000Mbps mode, the data bus carries transmit data at double data rate and are sampled on both the rising and falling edges of the transmit clock. In RGMII and RMII 10/100Mbps modes, the data bus is single data rate, synchronous to the rising edge of the transmit clock. Additionally in RMII 10Mbps mode, the data and control signals are held stable for 10 transmit clock cycles. The validity of the data is qualified with EMACn_TX_CTL.

EMAC<2:0>_TX_CTL 1 Output

This signal is driven by the EMAC component. In RGMII mode, this signal acts as the control signal for the transmit data, and is driven on both edges of the transmit clock, EMACn_TX_CLK.

Same clock to data relationships on CTL as with the data in the above row across the modes.

In RMII mode, this signal is high to indicate valid data.

EMAC<2:0>_RX_CLK 1 Input

In RGMII mode, this clock frequency is 125/25/2.5 MHz in 1 G/100 M/10 Mbps modes. It is provided by the external PHY. All PHY signals received by the EMAC are synchronous to this clock.

In RMII mode, this clock frequency is 50 MHz. The source of this clock can be:
  • An external source: In this case EMACn_TX_CLK must be left unconnected.
  • EMACn_TX_CLK: In this case, EMACn_TX_CLK must be connected to EMACn_RX_CLK.
1'b1 Pull-up
EMAC<2:0>_RXD[3:0] 4 Input

These data signals are received from the PHY. In RGMII 1000 Mbps mode, data is received at double data rate with bits[3:0] valid on the rising and falling edges of EMACn_RX_CLK. In RGMII 10/100Mbps modes, data is received at single data rate with bits[3:0] valid on the rising edge of EMACn_RX_CLK.

In RMII mode, data is received at single data rate with bits [1:0] valid on the rising edge of EMACn_RX_CLK. Additionally in RMII 10Mbps mode, the data and control signals are held stable for ten receive clock cycles. The validity of the data is qualified with EMACn_RX_CTL.

4'b1111 Pull-up
EMAC<2:0>_RX_CTL 1 Input

This signal is driven by the PHY and functions as the receive control signal used to qualify the data received on EMACn_RXD[3:0]. This signal is sampled on both edges of the clock in RGMII mode.

See row above for clock to data relationships across the modes.

1'b0 Pull-down