Agilex™ 7 Hard Processor System Technical Reference Manual

ID 683567
Date 8/13/2024
Public
Document Table of Contents

7.3.3. FPGA-to-HPS Bridge Signals

Table 69.   FPGA-to-HPS Bridge Signals
Name Direction Description
f2h_axi_clock Input Clock source from FPGA.
f2h_axi_reset Input Module reset signal from Reset Manager.
fpga2hps_enable Input To enable the FPGA-to-HPS Bridge from MPFE Interconnect.
fpga2hps_cmd_idle Output Indicates that the AW and AR channels are idle.
fpga2hps_force_drain Input Forces B and R channels to be flushed.
fpga2hps_resp_idle Output Indicates that the B channel and R channel are idle.
f2s_0_port_size_config[1:0] Input Port width configuration signal from FPGA:
  • 00: 128-bit
  • 01: 256-bit
  • 10: 512-bit
  • 11: Reserved