Agilex™ 7 Hard Processor System Technical Reference Manual

ID 683567
Date 8/13/2024
Public
Document Table of Contents

23.4.5.1. Clearing the Interrupt

An active timer interrupt can be cleared in two ways.

  1. If you clear the interrupt at the same time as the timer reaches 0, the interrupt remains asserted. This action happens because setting the timer interrupt takes precedence over clearing the interrupt. †
  2. To clear an active timer interrupt, read the timer1eoi register or disable the timer. When the timer is enabled, its interrupt remains asserted until it is cleared by reading the timer1eoi register. †