Agilex™ 7 Hard Processor System Technical Reference Manual

ID 683567
Date 8/13/2024
Public
Document Table of Contents

3.5.1.2. Security Model

The Arm* Cortex* -A53 processor implements all of the exception levels. The EL3 exists only in the secure state and a change from the secure state to the non-secure state is made only by an exception return from EL3. EL2 exists only in non-secure state.

Figure 3. Security Model when EL3 is using AArch64