Agilex™ 7 Hard Processor System Technical Reference Manual
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13.1.1.4. HPS Mailbox-triggered Cold Reset
If the cold reset is generated from internal sources (for example, a Mailbox command from the HPS software), the SDM switches this pin to output and drives a pulse to indicate reset. At this point, referring to the Agilex™ 7 Configuration User Guide, the bitstream configuration file containing the FSBL must be resent to the SDM using the same interface that the MSEL[2:0] pins specified during POR. Once the cold reset procedure is complete, this pin is switched back to input and can be pulled high by the external pull-up resister. Note that the FPGA is not disturbed during this process. The following figure shows the HPS Mailbox-triggered cold reset behavior.